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| Title of paper:
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Generalized net model of the discrete part manufacturing process of CMOS integrated circuit wafers
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| Author(s):
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| Sotir Sotirov
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| University “Prof. D-r Assen Zlatarov” – Bourgas, Bulgaria
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| ssotirov@btu.bg
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| Presented at:
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4th IWGN, Sofia, 23 September 2003
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| Published in:
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Conference proceedings, pages 61—67
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| Download:
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 PDF (175 Kb, File info)
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| Keywords:
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Generalized nets, Integrated circuit wafers
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| References:
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- Atanassov, K. Generalized Nets, World Scientific. Singapore, New Jersey, London, 1991.
- Atanassov, K., Introduction in the theory of the generalized nets, Pontika-Print, Bourgas, 1992.
- Haykin, S, Neural network and comprehensive foundation, Prentice Hall, New Jersey, 1999.
- Howard Demuth, Mark Beale, Neural network design, Prentice hall, New Jersey, 1995.
- Atanasov Kr., E. Sotirova, On global Operator G21 defined over Generalized Nets, Cybernetics and information technologies, Volume 4 No 2, Bulgarian Academy of Science, Sofia, 2004.
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| Citations:
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